Ratemeter

ABSTRACT

An instantaneous reading tachometer in which reoccurring events to be measured in rate, trigger a three-state timing generator in which the first two states are of fixed duration and the third state is of variable duration. An electrical decay circuit is set to a reference level by the second state and the third state causes this reference level to decay until the re-occurrence of an event. This triggers a new first state which in turn triggers a sample and hold circuit to hold the decayed level. The decayed level is amplified and provided as an output indicative of the instantaneous rate of occurrence of the last two successive events.

[miffed SidiQS Faterat n 1 Currie et al.

[ RATEMETER [75] inventors: James R. Currie. Ralph R. Kissell,

both of Huntsville, Ala.

[22] Filed: July 13, 1971 [21] Appl. No.: 162,101

[52] US. Cl. ..324/78 E, 128/206 F [51] int. Cl. ..G0lr 23/02, A6lb 5/04[58] Field of Search ..324/78 R, 78 E, 78 J,

[5 6] References Cited UNITED STATES PATENTS 3,614,634 l0/l97l Jones etal ..328/l40 ECG SOURCE {ill 3,729,676

Apr.2-t,1973

Primary Examine rAlfred E. Att0rney -L. D. Wofford, Jr. et al.

[57] ABSTRACT An instantaneous reading tachometer in which reoccurringevents to be measured in rate, trigger a threestate timing generator inwhich the first two states are of fixed duration and the third state isof variable duration. An electrical decay circuit is set to a referencelevel by the second state and the third state causes this referencelevel to decay until the re-occurrence of an event. This triggers a newfirst state which in turn triggers a sample and hold circuit to hold thedecayed level. The decayed level is amplified and provided 'as an outputindicative of the instantaneous rate of occurrence of the last twosuccessive events.

4 Claims, 3 Drawing Figures DECAY C l r 54 '35 4o HOLD HEART RATE I immcAToR Millcn 128/205 l Patented April 24, 1973 I 3 Shoots-Sheet l1355? Pia .Efi: w

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wudjow mum INVENTORS JAMES R. CURRIE RALPH R. KISSEL Patented April 24,1973 3 Sheets-Sheet 2 J01 F3 30 D arr m C Duds f uwD PDnFrD O m 85w d3:mik

Patented April 24, 1973 3 Sheets-Sheet 5 28.40.05 P55 .PN4MI m UEINVENTORS JAMES R. CURRIE RALPH R. KISSEL RATEMETER ORIGIN OF THEINVENTION The invention described herein was made by employees of theUnited States and may be manufactured and used by or for the Governmentof the United States of America for Governmental purposes without thepayment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION This invention relates to rate measurementdevices or tachometers and particularly to an improved tachometercapable of instantaneous rate measurement of relatively low rateoccurrences.

GENERAL DESCRIPTION OF THE PRIOR ART Heretofore the electricalmeasurement of the rate of occurrence of re-occurring events hasgenerally included the process of developing a pulse of a constant widthand amplitude for each occurrence of an event and then the pulses soobtained charge a capacitor connected in a relatively long time constantcircuit. The resulting voltage on the capacitor thus varies with thenumber of pulses applied to the capacitor within a predetermined timeand thus there is developed a voltage which may be measured to give anindication of average rate of occurrence of the pulses and thus the rateof occurrence of the events. The difficulty with this approach is thatit is not capable of providing an accurate rate output after theoccurrence of only a relatively few events and there are instances inwhich there exists a need to provide an essentially instantaneous rateoutput, that is after the occurrence of only two or three such events.For example, it is often necessary or desirable in the measurement ofheart rate to provide an instantaneous indication after the observationof only two or three heart beats, or to give continually updatedbeat-by-beat rate information. An alternate approach is to employdigital circuitry wherein events would be counted and the time measuredbetween two or more succeeding counts. The disadvantage of this approachis that the circuitry is fairly complex.

SUMMARY OF THE INVENTION Accordingly, it is an object of this inventionto' provide an improved rate measurement system capable of instantaneousmeasurements with a relatively simple combination of electrical circuitelements.

A further object of this invention is to provide an improved ratemeasurement system particularly adapted for the measurement on abeat-by-beat basis of heart rate.

These and other objects, features and advantages are accomplished in thepresent invention which encompasses an electronic system employing anevent sensor, a three-state pulse generator, a decay circuit and asample and hold circuit. The three states of the pulse generator arethree voltage levels, the first and second of which last forpredetermined periods. The duration of the third state is variable, itbeing cut off on the occurrence of a sensed event. For purposes ofdescription, we will assume that a complete cycle has occurred and thustwo events, the rate of occurrence of which it is desired to bemeasured, have occurred and there has occurred a full cycle of the threestates. The occurrence of the first event triggers the pulse generatorand a first state or voltage level is provided. It functions to causethe decay circuit to hold the value which it had reached by a previouscycle. Next and upon the occurrence of the second voltage state thedecay circuit is reset to a reference voltage which is held until theoccurrence of the third state after which this voltage is permitted todecay as a function of time until the occurrence of the next sensedevent. When this occurs the pulse generator switches the decay circuitto hold decayed level," which level is fed to the sample and holdcircuit which stores this voltage and provides it as an outputrepresentative of the rate of occurrence of the last two events.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an electrical block diagramof an embodiment of the invention.

FIG. 2 shows a series of graphs illustrative of operation of theembodiment of the invention shown in FIG. 1.

FIG. 3 is an electrical schematic diagram of certain of the circuitryshown in block form in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 illustrates broadly theinvention as applied to a heart rate monitor. An ECG signal 10 isobtained in a conventional manner from a patient, represented by ECGsource 12, and applied to ECG amplifier 14 which includes an appropriatefeedback circuit to intensify the R portion of the ECG waveforms. TheECG output of amplifier 14 is fed to pulse generator 16 which generatesa narrow negative pulse output 18 corresponding in time to the R portionof waveform 10. Three successive such pulses are shown in FIG. 2a andare labeled 18a, 18b and 180.

In response to a negative pulse 18, FIG. 2a, timing circuit 20 generatesa three state or level waveform 21 consisting of three discrete levels22, 24 and 26 (FIG. 2b). As shown, the first of these levels, level 22,is in the form of a negative pulse which lasts for 183 milliseconds. Thesecond level 24 is in the form of a positive pulse and it lasts for 117milliseconds. Depending upon the rate to be counted, the first andsecond levels would each be ofa duration of l to 2000 milliseconds.

The third level 26 is at zero level and its duration is variable, itcommencing at the end of positive pulse 24 and terminating on theoccurrence of the next sensed event or pulse 18. As shown, the firstseries of pulses are labeled with the suffix a, the second by the suffixb and the thirdby the suffix c. Decay circuit 28 is controlled by theoutput of timing circuit 20 and it provides output waveform 29 moreparticularly shown in FIG. 2c. As will be noted, it is activated at theend of each negative level or pulse-22 by an output from timing circuit20 to establish a reference voltage level 30 which lasts for theduration of positive pulse 24 (FIG. 2b). At the end of pulse 24, thisreference voltage is permitted to decay, as decay voltage 32, until theoccurrence of the next event and a pulse 18b. Pulse 18b then triggersnegative pulse 22b which in turn causes the instantaneous level of decayvoltage 32a to be held as level 34a for the duration of negative pulse22b.

Sample and hold circuit 31 functions to sample the output of decaycircuit 28 during held decayed levels 34 and to provide an output 35proportional to the value of held decayed level 34 to heart rateindicator 36. Sample and hold circuit 31 basically consists of sampleamplifier 38, hold amplifier 40, hold capacitor 42 and discharge circuit44. During the periods of negative pulses 22, the output of decaycircuit 28, represented by held decayed level 34, is applied as an inputto sample amplifier 38 and it in turn applies a charging current throughdiode 45 to capacitor 42 which charges capacitor 42 to the held decayedlevel. If the charge on capacitor 42 (from the last sample) shouldhappen to be higher than the present input level of amplifier 40,discharge circuit 44 consisting of Zener diode 46, resistor 48 and diode50 provide a unidirectional discharge path back to the output terminalof timing circuit 20, which path is effective during negative outputpulse 22. This discharges capacitor 42 to a level sufficiently low toinsure that capacitor 42 will respond to the new charge applied to it.Thevalue of resistor 48 and characteristic of Zener diode 46 are chosenso that the maximum discharge of capacitor 42 will be no more than 50percent of the maximum voltage developed across resistor 48 and this isadequate to permit a drop from sampling to sampling representative of200 to 40 beats per minute.

Hold amplifier 40 amplifies and couples the output of capacitor 42 torate indicator 36 which is an electrical voltmeter or other appropriatereadout calibrated in terms of heart rate. Feedback resistor 52 betweenthe output of hold amplifier 40 and input of sample amplifier 38 insuresthe proper level of charge on capacitor 42. Feedback resistor 54connects between the output and input of hold amplifier 40 and insuresthe accuracy of operation of hold amplifier 40. The value of resistor 54is chosen to provide a desired operating range for hold amplifier 40 andin the present case the'output is selected to have a range of zero tofive volts,

representative of a heart rate of 40 to 200 beats per minute and heartrate indicator 36 is so calibrated. At the end of the sample time, pointin time 56 (FIG. 2d), the output of hold amplifier 40 remains at thelevel determined by capacitor 42 until the next sample pulse. It will benoted that the vertical scale of FIG. 2d is substantially enlarged andthus the decay in voltage due to circuit loss between sampled outputs ofdecay circuit 28 are extremely small and thus the only significantchanges in output will be those determined by the output of decaycircuit 28 indicating a change in sensed rate.

Timing circuit 20, decay circuit 28 and sample and hold circuit 31 areshown in greater detail in FIG. 3 and will be further described withrespect to these figures.

Timing circuit 20 must perform a complex function. First it must have anegative state for the sample and hold phase. then it must have apositive state to reset decay circuit 28 to a maximum and finally itmust return to a zero state at precisely 300 milliseconds from the startof the cycle. The 300 milliseconds is the period for a heart rate of 200beats per minute. Amplifier 60 of timing circuit 20 is a standard typeLM709 integrated circuit, differential, operational amplifier. The inputcircuit of one input, pin 3, includes input diode 62, and capacitor 64in series with input resistor 66,

8 pin 6 and common terminal 67 and through resistor 72 to pin 3.Transistor 74 is employed to selectively short resistor 70, resistorbeing connected across the emitter-collector circuit of transistor 74.A-base input operating bias is applied to the base of transistor 74through resistor 76. The second input of amplifier 60,

pin 2, is connected through series resistor 78 and capacitor 80 tocommon terminal 67. A negative feedback path from output pin 6 isprovided through resistors 82 and 84 to pin 2 and the emitter-collectorcircuit of transistor 86 is connected across resistor 78 to provide forthe selective accelerated discharge of capacitor 80. The base input oftransistor 86 is driven through resistors 82 and 88 from pin 6.

Series connected capacitor 90 and resistor 92 provide desired inputfrequency compensation and are connected between pins 1 and 8 ofamplifier 60. Capacitor 94 is connected between pins 5 and 6 to providedesired output frequency compensation. Positive source terminal 96connects directly to pin 7, through resistor 76 to the base oftransistor 74 and through resistor 98 to pin 6 of amplifier 60. Negativesource terminal 100 connects directly to pin 4 of amplifier 60.

To consider the operation of timing circuit 20, it will be noted thatprior to the application of an input pulse, the voltage at input pins 2and 3 and output pin 6 of amplifier 60 are all at a zero level. With azero potential on the collector of transistor 74, it is not operatingand similarly with no base or collector voltage on transistor 86 it isnot operating. Upon the application of the first negative pulse 18a(FIG. 2a) through capacitor 64 to negative input pin 3, the voltage onoutput pin 6 is caused to change in a negative direction. It is to benoted that the output on pin 6 is in phase with the input on pin 3 andout of phase with the input on pin 2. The negative going signal on pin 6is fed back through resistors 68 and 72 as a positive feedback to pin 3causing regeneration in amplifier 60 to rapidly saturate it as shown bynegative output pulse or level 22a (FIG. 2b). This negative output atpin 6 is fed as negative feedback through resistors 82 and 84 to inputpin 2 and through resistor 78 to capacitor 80. Neither transistors 74 or86 are affected by the negative output or level 22a.

As a result of the feedback circuit to pin 2 and to capacitor 80, thevoltage at pin 2, initially at zero, changes in a negative direction ascapacitor 80 charges. When the negative voltage on pin 2 exceeds that ofthe negative voltage on pin 3, the differential input to amplifier 60reverses in polarity and pin 3 becomes-positivewith respect to pin 2.This causes the output on pin 6 to change in a positive direction,rising toward zero. By virtue of the positive feedback from pin 6 to pin3 the rising voltage on pin 3 causes the output voltage on pin 6 torapidly rise through zero to its saturated positive level 24a. As thevoltage on pin 6 rises above zero it causes transistor 74 to beenergized and resistor 70 to be shorted out pulling the potential on pin3 to zero.

Thus at the beginning of level 24a there exists a zero potential on pin3 (which value remains on pin 3 for the duration of level 24a), anegative potential, approximately 5 volts, on capacitor 80 and on pin 2,and a maximum positive potential on pin 6. With a negative potential oncapacitor 80 and a positive potential on pin 6 of amplifier 60 anoperating bias is applied to transistor 86, t0 the collector throughresistors 82 and 84 and to the base through resistors 82 and 88 (withrespect to common terminal 67). This results in resistor 78 beingshorted out and capacitor 80 to commence discharging through a firstdischarge path consisting of resistors 82 and 84 and a second dischargepath through resistor 82, resistor 88, and the base-emitter circuit oftransistor 86. This is a lower impedance path than existed during thecharging of capacitor 80 with the result that the discharge of capacitor80 is accelerated. As a result the voltage at pin 2 rises to near zeroin 1 17 milliseconds. When this occurs amplifier 60 is pulled out ofsaturation and by virtue of negative feedback from pin 6 to pin 2 theoutput level is rapidly pulled down to zero potential or level 26a asshown in V FIG. 2b after a period of a few microseconds. Level 26a willbe retained until the occurrence of pulse 18b and thus there has justbeen described a complete cycle of operating of timing circuit 20. Pulse18b triggers pulse 22b and thereafter pulses 24b and 26b occur in'themanner just described.

Decay circuit 28 is driven by an output on pin 6 of amplifier 60 oftiming circuit 20. The input to decay circuit 28 is polarized by diode104 to permit passage of only a positive pulse or level 24 which isapplied through resistor 106 to the base of transistor 108 and throughresistor 110 to the base of transistor 112. Re-

sistor 113 divides the input voltage to transistor 112 to a selectedoperating level. A reference potential is provided across Zener diode114 which is connected to positive terminal 96 through resistor 116.When operated on, transistor 108 applies this reference potential tocapacitor 118. While there is also created a circuit through resistor120 to capacitor 122, since transistor 112 is turned on at the sametime, no charge is applied to capacitor 122. Transistor 124 provides aselective discharge path for capacitor 118 through resistor 126, andtransistor 127 provides a selective discharge path for capacitor 122.Transistors 124 and 127 are simultaneously switched by voltage dividers128 and 129, respectively, connected between positive terminal 96through diode 130 back to pin 6 of amplifier 60 of timing circuit 20.The base of transistor 124 is connected between series resistors 132 and134 of voltage divider 128 and the base of transistor 127 is connectedbetween series connected resistors 136 and 138 of voltage divider 129.By means of this circuitry,

transistors 124 and 127 are turned off during the negacapacitor 118. Atthe termination of level 24a, transistors 108 and 112 turn off andcapacitor 118 starts its decay through resistor 126 and on transistor124. Transistors 124 and 127 are on when the level on pin 6 of amplifier60 is either zero or positive and off when this level is negative. Therole of capacitor 122 is to linearize decay and improve the accuracy ofthe system. Initially, during the decay, it receives a charge throughresistor (transistor 112 now being turned off) as capacitor 118discharges. At a desired point in the discharge of capacitor 118,capacitor 122 ceases charging and commences to discharge and thus slowsthe decay of voltage on capacitor 118. The process is abruptly stoppedupon the occurrence of negative pulse 18b to cause the output level ofamplifier 60 to go negative to level 22b, causing diode to fully conductand sufficiently lower the base potential on transistors 124 and 127 toturn them off. This point is indicated by point 141 of FIG. 2c, whichmarks the beginning of held decayed level" 34a, which is the usefuloutput of decay circuit 28. During other intervals, when the outputlevels of timing circuit 20 are either zero or positive, transistor 124is turned on and thus the output of decay circuit 28, at the collectorof transistor 124, is zero.

Sample and hold circuit 31 consists basically of sample amplifier 38,hold amplifier 40 and storage capacitor 42. The sample and holdamplifiers are identical to amplifier 60 of timing circuit 20 and arebiased in a like capacitor 152 connected in series between pins 1 and 8and an output frequency compensation capacitor 154 connected betweenterminals 5 and 6. A diode limiter 156 is connected across inputterminals 2 and 3 of sample amplifier 38, and oppositely connecteddiodes 158 and 160 limit the magnitude, positive or. negative, ofsignals applied between terminals 2 and 3 of amplifier 40. A referenceinput to pin 2 of amplifier 38 is applied from positive terminal 96through resistors 116, 162 and 164. A feedback connection is providedfrom pin 6 of hold amplifier 40 back through resistors 166 and 164 topin 2 of sample amplifier 38 and resistor 54 is connected in a feedbackloop from the pin 6 output to the pin 2 input of hold amplifier 40.Output pin 6 of sample amplifier 38 is connected through resistor 166and diode 45 to the pin 3 input of hold amplifier 40. Storage or holdcapacitor 42 is connected between pin 3 of amplifier 40 and commonterminal 67 and serves to provide a holding or storage function forsample and hold circuit 31. Zener diode 46 and resistor 48 in serieswith diode 50 serve to reduce, as explained above, the voltage oncapacitor 42 to a level sufficiently low to insure that capacitor 42will be appropriately charged despite rapid decreases in levelsrepresented by rapid decreases in input rate to the system.

To consider the operation of sample and hold circuit 31 it will beassumed that negative pulse 22a (FIG. 2b) hasjust been initiated and theoutput level 34 (FIG. 2c) is applied to pin 3 of sample amplifier 38.Since transistors 124 and 127 of timing circuit 28 have been turned offby pulse 220, as explained above, the potential or level 34 on capacitor1 18 is held for the duration of pulse 22a. With this held level or helddecayed level" 34 applied to pin 3 of sample amplifier 38, there is alike or proportional output on output pin 6 of sample amplifier 38 whichis applied through resistor 166 and diode 45 to pin 3 of hold amplifier40 and thus across storage capacitor 42. Storage capacitor 42 is ofarelatively large value, on the order of 10 microfarads, and it assumesthe output voltage of amplifier 38. Negative feedback provided throughresistors 166 and 164 assure that amplifiers 38 and 40 will have astable gain and provide a linear output and thus an extremely accurateoutput. The output of hold amplifier 40 is fed through resistor 168 andappears across resistor 170 and is fed to heart rate indicator 36. Asdescribed above, the output of hold amplifier 40 has a range of zero tofive volts, representative of a heart rate of 40 to 200 beats per minutewhich is indicated by rate indicator 36.

The cycle of operation just described repeats with each input pulse 18and the output rate indicated by heart rate indicator 36 is that of there-occurrence rate of the last two occurring events.

While this invention is believed particularly useful in its applicationto heart rate measurement systems it is to be appreciated that it hasapplication to rate measurements in general, particularly where there isa need for the accurate, instantaneous measurement of rates belowapproximately 2,000 events per second.

What is claimed is: 1. A ratemeter comprising: A. sensing meansresponsive to re-occurring events, for providing an electrical output,timing, pulse of a first polarity upon the occurrence of each event;

B. timing means responsive to each said output pulse of said sensingmeans for providing, successively, and on a reoccurring basis, first,second and third discrete electrical levels, said first and secondelectrical levels being of predetermined duration and the duration ofsaidthird level being equal to the period between said output pulsesless the total duration of said first and second electrical levels, andwherein said timing means comprises:

1. a differential amplifier having a first input, a second input and anoutput, said first input and said output being of like phase and saidsecond input being of opposite phase to that of said outp 2. firstcircuit means connecting a portion of the output voltage present on saidoutput to said first input and including first switching means connectedto said first input and responsive to a second polarity output of saidamplifier for shorting said first input,

3. second circuit means comprising:

a capacitor having one terminal connected to a reference potential,

a resistor connected between the other terminal of said capacitor andsaid second input,

a circuit connecting said output through said resistor to saidcapacitor, and

second switching means connected across said resistor and responsive toa second polarity output of said amplifier for shorting said resistorbetween said capacitor and said second input,

whereby with an initial condition of zero voltage on said inputs thereexists a zero voltage as said third discrete electrical level on saidoutput,

a said first polarity timing pulse applied to said first input causessaid amplifier to provide a maximum first polarity output, or firstdiscrete electrical level, which output is coupled to said capacitorwhich commences charging in a first polarity direction to provide anincreasing amplitude first polarity input to said second input andtiming the duration of said first discrete electrical level,

when the level of said first polarity voltage on said second inputexceeds the level on said first input the differential input of saidamplifier switches polarity and the potential on said output changes toa maximum second polarity value as said second discrete electricallevel, and

said second switching means is operated by said second polarity fromsaid output shorting said resistor and causing said capacitor tocommence discharging, timing said second discrete electrical level, andwhen the voltage on said second input is pulled down to a point whichcauses the differential amplifier to abruptly change from said secondelectrical discrete level to a neutral state with a zero output, saidthird discrete electrical level is provided on said output, which levelremains until the re-occurrence ofa said timing pulse;

C. decay circuit means responsive to the output of said timing meansand-to the initiation of said second electrical level for establishing areference voltage and including time constant means responsive to theinitiation of said third level for providing a voltage which initiallycorresponds to said reference voltage, then decays during said thirdelectrical level to a decayed level, and including means responsive tothe next occurring said first electrical level for halting said decayand holding the decayed level for the duration of said next occurringfirst electrical level; and

D. sample and hold means responsive to said decay circuit means and saiddecayed level for providing a substantially continuously level outputproportional to the last held decayed level and which is representativeof the rate of occurrence of the last two successive said events.

2. A ratemeter as set forth in claim 1 wherein the duration of saidfirst electrical level is between 1 and 2000 milliseconds and theduration of said second electrical level is between l and 2000milliseconds.

3. A ratemeter as set forth in claim 1 wherein said first electricallevel is of a positive potential, said second electrical level is of anegative potential and said third electrical level is of a zeroelectrical potential.

4. A ratemeter as set forth in claim 1 wherein said decay circuit meanscomprises means for providing an output which is equal to said decayedlevel during said first electrical level and is substantially zeroduring said second and third electrical levels.

1. A ratemeter comprising: A. sensing means responsive to re-occurringevents, for providing an electrical output, timing, pulse of a firstpolarity upon the occurrence of each event; B. timing means responsiveto each said output pulse of said sensing means for providing,successively, and on a reoccurring basis, first, second and thirddiscrete electrical levels, said first and second electrical levelsbeing of predetermined duration and the duration of said third levelbeing equal to the period between said output pulses less the totalduration of said first and second electrical levels, and wherein saidtiming means comprises:
 1. a differential amplifier having a firstinput, a second input and an output, said first input and said outputbeing of like phase and said second input being of opposite phase tothat of said output,
 2. first circuit means connecting a portion of theoutput voltage present on said output to said first input and includingfirst switching means connected to said first input and responsive to asecond polarity output of said amplifier for shorting said first input,3. second circuit means comprising: a capacitor having one terminalconnected to a reference potential, a resistor connected between theother terminal of said capacitor and said second input, a circuitconnecting said output through said resistor to said capacitor, andsecond switching means connected across said resistor and responsive toa second polarity output of said amplifier for shorting said resistorbetween said capacitor and said second input, whereby with an initialcondition of zero voltage on said inputs there exists a zero voltage assaid third discrete electrical level on said output, a said firstpolarity timing pulse applied to said first input causes said amplifierto provide a maximum first polarity output, or first discrete electricallevel, which output is coupled to said capacitor which commencescharging in a first polarity direction to provide an increasingamplitude first polarity input to said second input and timing theduration of said first discrete electrical level, when the level of saidfirst polarity voltage on said second input exceeds the level on saidfirst input the differential input of said amplifier switches polarityand the potential on said output changes to a maximum second polarityvalue as said second discrete electrical level, and said secondswitching means is operated by said second polarity from said outputshorting said resistor and causing said capacitor to commencedischarging, timing said second discrete electrical level, and when thevoltage on said second input is pulled down to a point which causes thedifferential amplifier to abruptly change from said second electricaldiscrete level to a neutral state with a zero output, said thirddiscrete electrical level is provided on said output, which levelremains until the re-occurrence of a said timing pulse; C. decay circuitmeans responsive to the output of said timing means and to theinitiation of said second electrical level for establishing a referencevoltage and including time constant means responsive to the initiationof said third level for providing a voltage which initially correspondsto said reference voltage, then decays during said third electricallevel to a decayed level, and including means responsive to the nextoccurring said first electrical level for halting said decay and holdingthe decayed level for the duration of said next occurring firstelectrical level; and D. sample and hold means responsive to said decaycircuit means and said decayed level for providing a substantiallycontinuously level output proportional to the last held decayed leveland which is representative of the rate of occurrence of the last twosuccessive said events.
 2. first circuit means connecting a portion ofthe output voltage present on said output to said first input andincluding first switching means connected to said first input andresponsive to a second polarity output of said amplifier for shortingsaid first input,
 2. A ratemeter as set forth in claim 1 wherein theduration of said first electrical level is between 1 and 2000milliseconds and the duration of said second electrical level is between1 and 2000 milliseconds.
 3. A ratemeter as set forth in claim 1 whereinsaid first electrical level is of a positive potential, said secondelectrical level is of a negative potential and said third electricallevel is of a zero electrical potential.
 3. second circuit meanscomprising: a capacitor having one terminal connected to a referencepotential, a resistor connected between the other terminal of saidcapacitor and said second input, a circuit connecting said outputthrough said resistor to said capacitor, and second switching meansconnected across said resistor and responsive to a second polarityoutput of said amplifier for shorting said resistor between saidcapacitor and said second input, whereby with an initial condition ofzero voltage on said inputs there exists a zero voltage as said thirddiscrete electrical level on said output, a said first polarity timingpulse applied to said first input causes said amplifier to provide amaximum first polarity output, or first discrete electrical level, whichoutput is coupled to said capacitor which commences charging in a firstpolarity direction to provide an increasing amplitude first polarityinput to said second input and timing the duration of said firstdiscrete electrical level, when the level of said first polarity voltageon said second input exceeds the level on said first input thedifferential input of said amplifier switches polarity and the potentialon said output changes to a maximum second polarity value as said seconddiscrete electrical level, and said second switching means is operatedby said second polarity from said output shorting said resistor andcausing said capacitor to commence discharging, timing said seconddiscrete electrical level, and when the voltage on said second input ispulled down to a point which causes the differential amplifier toabruptly change from said second electrical discrete level to a neutralstate with a zero output, said third discrete electrical level isprovided on said output, which level remains until the re-occurrence ofa said timing pulse; C. decay circuit means responsive to the output ofsaid timing means and to the initiation of said second electrical levelfor establishing a reference voltage and including time constant meansresponsive to the initiation of said third level for providing a voltagewhich initially corresponds to said reference voltage, then decaysduring said third electrical level to a decayed level, and includingmeans responsive to the next occurring said first electrical level forhalting said decay and holding the decayed level for the duration ofsaid next occurring first electrical level; and D. sample and hold meansresponsive to said decay circuit means and said decayed level forproviding a substantially continuously level output proportional to thelast held decayed level and which is representative of the rate ofoccurrence of the last two successive said events.
 4. A ratemeter as setforth in claim 1 wherein said decay circuit means comprises means forproviding an output which is equal to said decayed level during saidfirst electrical level and is substantially zero during said second andthird electrical levels.